PALcode (Privileged Architecture Library code) is a set of functions in the SRM or ARC (AlphaBIOS) firmware, providing a hardware abstraction layer for system software, covering features such as cache management, translation lookaside buffer (TLB) miss handling, interrupt handling, exception handling, debugging (breakpoint handling), process scheduling, CPU halting, (re)booting.
PALcode instructions can be:
PALcode is Alpha machine code, running in a special mode that allows access to internal registers specific to the particular Alpha processor implementation. The PALcode is running with interrupts disabled. As a consequence multi-instruction code sequences run as atomic operations. It is thus somewhere between the role of microcode and of a hardware emulator.
Alpha instructions are always 32-bit, to simplify instruction decoding, and execution. Lowcost systems can implement single path instruction fetching, over a 64-bit internal data path, while high speed processors can fetch instructions in parallel over a 128-bit internal data path.
PALcode is specific for each hardware implementation. It allows to create a standard runtime environment so that you can run identical software on all hardware models in the processor family. For certain lowcost CPUs, infrequently used instructions can be implemented in software. For the high range processors, more instructions are implemented in hardware, to increase the execution speed.
In a real AlphaServer, the PALcode is stored in the PAL (Programmable Array Logic) EPROM, which is effectually hardware. However to support the different operating systems, there is a mechanism to overrule PALcode instructions in software (using a small dedicated part of main RAM memory).
In the emulator, PALcode is part of the SRM Firmware (containing both OpenVMS and Tru64 UNIX PALcode). Parts of the OpenVMS PALcode have been replaced with C++ code (member functions of CAlphaCPU named vmspal_xxx) for speed.