PIC

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Ali M1543C ISA Bus controller: PIC
Intel 8259
ClassCAliM1543C
Derived fromPCI Device
Connects toTyphoon chipset
HeaderAliM1543C.h
SourceAliM1543C.cpp
List of all devices

Functional Description

The Programmable Interrupt Controller is part of the ISA controller, which in turn is a part of the Ali M1543C southbridge chip. The Interrupt controller is compatible with the Intel 82C59[1] PIC.

The 8259 acts as a multiplexer, combining multiple interrupt input sources into a single interrupt output to interrupt a single device.

Connections

The main connectors on an 8259 are as follows: eight interrupt input request lines named IRQ0 through IRQ7, an interrupt request output line named INTR, interrupt acknowledgment line named INTA, D0 through D7 for communicating the interrupt level or vector offset. Other connectors include CAS0 through CAS2 for cascading between 8259s.

Up to eight slave 8259s may be cascaded to a master 8259 to provide up to 64 IRQs. 8259s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one master 8259.

Registers

There are three registers, an Interrupt Mask Register (IMR), an Interrupt Request Register (IRR), and an In-Service Register (ISR). The IRR maintains a mask of the current interrupts that are pending acknowledgement, the ISR maintains a mask of the interrupts that are pending an EOI, and the IMR maintains a mask of interrupts that should not be sent an acknowledgement.

End Of Interrupt (EOI) operations support specific EOI, non-specific EOI, and auto-EOI. A specific EOI specifies the IRQ level it is acknowledging in the ISR. A non-specific EOI resets the IRQ level in the ISR. Auto-EOI resets the IRQ level in the ISR immediately after the interrupt is acknowledged.

Fixed priority and rotating priority modes are supported.

Edge/Level Triggered Mode

Since the ISA bus does not support level triggered interrupts, level triggered mode may not be used for interrupts connected to ISA devices. This means that on PC/XT, PC/AT, and compatible systems the 8259 must be programmed for edge triggered mode. On newer PCI systems the Edge/Level Control Registers (ELCRs) control the mode per IRQ line, effectively making the mode of the 8259 irrelevant for such systems with ISA buses. The ELCR is programmed by the BIOS at system startup for correct operation.

The ELCRs are located 0x4d0 and 0x4d1 in the x86 I/O address space. They are 8-bits wide, each bit corresponding to an IRQ from the 8259s. When a bit is set, the IRQ is in level triggered mode; otherwise, the IRQ is in edge triggered mode.

Interrupt connections

The Ali chip has two 8259 controllers, master and slave. IRQ0 through IRQ7 are the master 8259's interrupt lines, while IRQ8 through IRQ15 are the slave 8259's interrupt lines.

  • Slave 8259
    • IRQ8 – TOY Clock
    • IRQ9 –
    • IRQ10 –
    • IRQ11 –
    • IRQ12 – Mouse controller
    • IRQ13 –
    • IRQ14 – IDE controller 1
    • IRQ15 – IDE controller 2

References

  1. Intel 8259A Datasheet at location 1, location 2

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