PIT

From ES40 Emulator
Jump to: navigation, search
Ali M1543C ISA Bus controller: PIT
8253
ClassCAliM1543C
Derived fromPCI Device
Connects toTyphoon chipset
HeaderAliM1543C.h
SourceAliM1543C.cpp
List of all devices

Functional Description

The Programmable Interval Timer is part of the ISA controller, which in turn is a part of the Ali M1543C southbridge chip. The Interrupt controller is compatible with the Intel 82C53[1] PIT.

Features

The timer has three counters, called channels. Each channel can be programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ-0 on the PIC (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it.

Typical Components

Counters

There are 3 counters (or timers), which are labeled as Counter 0, Counter 1 and Counter 2. Each counter has 2 input pins - CLK (clock input) and GATE - and 1-pin, OUT, for data output. The 3 counters are 16-bit down counters independent of each other, and can be easily read by the CPU.

The first counter (selected by setting A1=A0=0, see Control Word Register below) helps generate an 18.2 Hz clock signal. The second counter (A1=0, A0=1) assists in generating timing, which will be used to refresh the DRAM memory. The last counter (A1=1, A0=0) generates tones for the PC speaker.

Control Word Register

This register contains the programmed information which will be sent (by the CPU) to the device. It defines how the PIT logically works.

To initialize the counters, the microprocessor must write a control word (CW) in this register.

The control word contains 8 bits, labeled D7..D0 (D7 is the most significant bit).

Bit#   D7  D6     D5  D4     D3 D2 D1      D0
Name  SC1 SC0    RW1 RW0     M2 M1 M0      BCD
----  --------   ----------  -----------   ------------------------
Func. Select     Read/Write  Select        =0, 16-b binary counter
      Counter                Mode          =1, 4-decade BCD counter

The following table describes how to use the Read/Write bits (RW1, RW0).

RW1   RW0   Description
---   ---   ------------------------------------------------
 0     0    Counter Latch Command
 0     1    Read/Write the least significant byte (LSB) only
 1     0    Read/Write the most significant byte (MSB) only
 1     1    Read/Write LSB first, followed by MSB 

Details about other bits will be provided in the next section.

When setting the PIT, the microprocessor first sends a control message, then a count message to the PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the rising edge from the GATE input signal.

The address for the Control Word Register is 043h, and 040h, 041h, 042h for each counter, respectively.

Operation Modes

The D3, D2, and D1 bits of the Control Word set the operating mode of the timer. There are 6 modes in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3. Notice that, for modes 0, 2, 3 and 4, GATE must be set to HIGH to enable counting. For modes 1 and 5, the rising edge of GATE starts the count.

Mode 0 (000): Interrupt on Terminal Count

In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency.

The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written.

Mode 1 (001): Hardware-Triggered One Shot

This is similar to mode 0, but counting is started by a rising edge on the GATE input instead of immediately after programming. The GATE input is ignored while counting.

The output is set high as soon as the Control Word is written. After COUNT is written, the device will wait until the rising edge of the GATE input. One clock cycle after this rising edge is detected, OUT will become and remain low until the counter reaches 0. OUT will then go high, waiting for the next trigger.

Mode 2 (x10): Rate Generator

In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time clock interrupt.

Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT will then remain high until the counter reaches 1, and will go low for one clock pulse. OUT will then go high again, and the whole process repeats itself.

The time between the high pulses depends on the preset count in the counter's register, and is calculated using the following formula:

Value to be loaded into counter = <math> {\it f_{input}} \over {\it f_{output}} </math>

Note that the values in the COUNT register range from <math>n</math> to 1; the register never reaches zero.

Mode 3 (x11): Square Wave Generator

This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output will be different.

Suppose n is the number loaded into the counter (the COUNT message), the output will be

  • high for n/2 counts, and low for n/2 counts, if n is even.
  • high for (n+1)/2 counts, and low for (n-1)/2</math> counts, if n is odd.

Mode 4 (100): Software Triggered Strobe

After Control Word and COUNT is loaded, the output will remain high until the counter reaches zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) - after that the output will become high again.

Mode 5 (101): Hardware Triggered Strobe

This mode is similar to mode 4. However, the counting process is triggered by the GATE input.

After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle - after that it will become high again, to repeat the cycle on the next rising edge of GATE.

References

  1. OKI 8253 Datasheet at location 1

Parts of this page come from WikiPedia