AlphaCPU.h File Reference

Detailed Description

Contains the definitions for the emulated DecChip 21264CB EV68 Alpha processor.

AlphaCPU.h,v 1.57 2008/03/24 21:47:50 iamcamiel Exp

X-1.57 Camiel Vanderhoeven 24-MAR-2008 Comments.

X-1.56 Camiel Vanderhoeven 14-MAR-2008 Formatting.

X-1.55 Camiel Vanderhoeven 14-MAR-2008 1. More meaningful exceptions replace throwing (int) 1. 2. U64 macro replaces X64 macro.

X-1.54 Camiel Vanderhoeven 13-MAR-2008 Create init(), start_threads() and stop_threads() functions.

X-1.53 Camiel Vanderhoeven 11-MAR-2008 Named, debuggable mutexes.

X-1.52 Camiel Vanderhoeven 05-MAR-2008 Multi-threading version.

X-1.51 Brian Wheeler 29-FEB-2008 Add BREAKPOINT INSTRUCTION command to IDB.

X-1.50 Camiel Vanderhoeven 08-FEB-2008 Show originating device name on memory errors.

X-1.49 Camiel Vanderhoeven 01-FEB-2008 Avoid unnecessary shift-operations to calculate constant values.

X-1.48 Camiel Vanderhoeven 30-JAN-2008 Always use set_pc or add_pc to change the program counter.

X-1.47 Camiel Vanderhoeven 30-JAN-2008 Remember number of instructions left in current memory page, so that the translation-buffer doens't need to be consulted on every instruction fetch when the Icache is disabled.

X-1.46 Camiel Vanderhoeven 29-JAN-2008 Cleanup.

X-1.45 Camiel Vanderhoeven 29-JAN-2008 Remember separate last found translation-buffer entries for read and write operations. This should help with memory copy operations.

X-1.44 Camiel Vanderhoeven 28-JAN-2008 Better floating-point exception handling.

X-1.43 Camiel Vanderhoeven 27-JAN-2008 Comments.

X-1.40 Camiel Vanderhoeven 27-JAN-2008 Minor floating-point improvements.

X-1.39 Camiel Vanderhoeven 25-JAN-2008 Added option to disable the icache.

X-1.37 Camiel Vanderhoeven 21-JAN-2008 Moved some macro's to cpu_defs.h; implement new floating-point code.

X-1.36 Camiel Vanderhoeven 19-JAN-2008 Run CPU in a separate thread if CPU_THREADS is defined. NOTA BENE: This is very experimental, and has several problems.

X-1.35 Camiel Vanderhoeven 18-JAN-2008 Comments.

X-1.34 Camiel Vanderhoeven 18-JAN-2008 Process device interrupts after a 100-cpu-cycle delay.

X-1.33 Camiel Vanderhoeven 08-JAN-2008 Removed last references to IDE disk read SRM replacement.

X-1.32 Camiel Vanderhoeven 02-JAN-2008 Endianess fix.

X-1.31 Camiel Vanderhoeven 02-JAN-2008 Comments. Undid part of last change because of performance impact.

X-1.30 Camiel Vanderhoeven 29-DEC-2007 Avoid referencing uninitialized data.

X-1.29 Camiel Vanderhoeven 17-DEC-2007 SaveState file format 2.1

X-1.28 Camiel Vanderhoeven 10-DEC-2007 Use configurator.

X-1.27 Camiel Vanderhoeven 2-DEC-2007 Changed the way translation buffers work, the way interrupts work, added vmspal routines.

X-1.26 Brian Wheeler 1-DEC-2007 Added support for instruction counting, underlined lines in listings, corrected some unsigned/signed issues.

X-1.25 Brian Wheeler 22-NOV-2007 Added set_r and set_f for LOADREG and LOADFPREG debugger commands.

X-1.24 Camiel Vanderhoeven 06-NOV-2007 Performance improvements to ICACHE: last result is kept; cache lines are larger (512 DWORDS in stead of 16 DWORDS), cache size is configurable (both number of cache lines and size of each cache line), memcpy is used to move memory into the ICACHE. CAVEAT: ICACHE can only be filled from memory (not from I/O).

X-1.23 Eduardo Marcelo Ferrat 31-OCT-2007 Disable SRM replacement routines.

X-1.22 Camiel Vanderhoeven 17-APR-2007 Give ASM bit a value (true) for PALmode Icache entries.

X-1.21 Camiel Vanderhoeven 11-APR-2007 Moved all data that should be saved to a state file to a structure "state".

X-1.20 Camiel Vanderhoeven 7-APR-2007 Added get_hwpcb;

X-1.19 Camiel Vanderhoeven 5-APR-2007 Fixed X-1.14. The virtual address was returned instead of the physical one!

X-1.18 Camiel Vanderhoeven 31-MAR-2007 Added old changelog comments.

X-1.17 Camiel Vanderhoeven 18-MAR-2007 Removed pointles comparison (v_prbr > 0).

X-1.16 Camiel Vanderhoeven 14-MAR-2007 bListing removed.

X-1.15 Camiel Vanderhoeven 12-MAR-2007 a) Added possibility to retrieve physical address of current instruction. b) Added member function get_pal_base.

X-1.14 Camiel Vanderhoeven 9-MAR-2007 Try to translate a virtual PRBR value to a physical one in get_prbr.

X-1.13 Camiel Vanderhoeven 8-MAR-2007 va_form now takes a boolean argument bIBOX to determine which ASN and VPTB to use.

X-1.12 Camiel Vanderhoeven 7-MAR-2007 Added get_tb, get_asn and get_spe functions.

X-1.11 Camiel Vanderhoeven 22-FEB-2007 Add ASM bit to the instruction cache & corresponding functions.

X-1.10 Camiel Vanderhoeven 18-FEB-2007 Add get_f function.

X-1.9 Camiel Vanderhoeven 16-FEB-2007 a) Added CAlphaCPU::listing. b) CAlphaCPU::DoClock now returns a value.

X-1.8 Camiel Vanderhoeven 12-FEB-2007 Added get_r and get_prbr functions as inlines.

X-1.7 Camiel Vanderhoeven 12-FEB-2007 Added inline functions to get and update the program counter (pc).

X-1.6 Camiel Vanderhoeven 12-FEB-2007 Added comments.

X-1.5 Camiel Vanderhoeven 9-FEB-2007 Added comments.

X-1.4 Camiel Vanderhoeven 9-FEB-2007 Moved debugging flags (booleans) to TraceEngine.

X-1.3 Camiel Vanderhoeven 7-FEB-2007 Added comments.

X-1.2 Brian Wheeler 3-FEB-2007 Formatting.

X-1.1 Camiel Vanderhoeven 19-JAN-2007 Initial version in CVS.

Definition in file AlphaCPU.h.

#include "SystemComponent.h"
#include "System.h"
#include "cpu_defs.h"

Go to the source code of this file.

Data Structures

class  CAlphaCPU
 Emulated CPU. More...
struct  CAlphaCPU::SCPU_state
 The state structure contains all elements that need to be saved to the statefile. More...
struct  CAlphaCPU::SCPU_state::SICache
 Instruction cache entry. More...
struct  CAlphaCPU::SCPU_state::STBEntry
 Translation Buffer Entry. More...


#define ICACHE_ENTRIES   1024
 Number of entries in the Instruction Cache.
#define ICACHE_LINE_SIZE   512
#define ICACHE_MATCH_MASK   (u64) (U64(0x1) - (ICACHE_LINE_SIZE * 4))
 These bits should match to have an Instruction Cache hit.
#define ICACHE_INDEX_MASK   (u64) (ICACHE_LINE_SIZE - U64(0x1))
 DWORD (instruction) number of an address in an ICache entry.
 Byte numer of an address in an ICache entry.
#define TB_ENTRIES   16
 Number of entries in each Translation Buffer.
#define RREG(a)
 Translate raw register (0.


bool bTB_Debug

Define Documentation


Byte numer of an address in an ICache entry.

Definition at line 228 of file AlphaCPU.h.

Referenced by CAlphaCPU::get_icache().

#define ICACHE_ENTRIES   1024

Number of entries in the Instruction Cache.

Definition at line 219 of file AlphaCPU.h.

Referenced by CAlphaCPU::flush_icache(), CAlphaCPU::flush_icache_asm(), and CAlphaCPU::get_icache().

#define ICACHE_INDEX_MASK   (u64) (ICACHE_LINE_SIZE - U64(0x1))

DWORD (instruction) number of an address in an ICache entry.

Definition at line 226 of file AlphaCPU.h.

Referenced by CAlphaCPU::get_icache().

#define ICACHE_LINE_SIZE   512

Definition at line 221 of file AlphaCPU.h.

Referenced by CAlphaCPU::get_icache().

#define ICACHE_MATCH_MASK   (u64) (U64(0x1) - (ICACHE_LINE_SIZE * 4))

These bits should match to have an Instruction Cache hit.

This includes bit 0, because it indicates PALmode .

Definition at line 224 of file AlphaCPU.h.

Referenced by CAlphaCPU::get_icache().


Definition at line 212 of file AlphaCPU.h.

#define RREG (  ) 


(                                                                    \
      ((a) & 0x1f) +                                                     \
        (((state.pc & 1) && (((a) & 0xc) == 0x4) && state.sde) ? 32 : 0) \
Translate raw register (0.

.31) number to a number that takes PALshadow registers into consideration (0..63). Considers the program counter (to determine if we're in PALmode), and the SDE (Shadow Enable) bit.

Definition at line 537 of file AlphaCPU.h.

Referenced by CAlphaCPU::get_r().

#define TB_ENTRIES   16

Number of entries in each Translation Buffer.

Definition at line 230 of file AlphaCPU.h.

Referenced by CAlphaCPU::add_tb(), CAlphaCPU::FindTBEntry(), CAlphaCPU::tbia(), and CAlphaCPU::tbiap().

Variable Documentation

bool bTB_Debug Logo
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