CAlphaCPU Class Reference

#include <AlphaCPU.h>

Inheritance diagram for CAlphaCPU:

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Collaboration diagram for CAlphaCPU:

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Detailed Description

Emulated CPU.

The CPU emulated is the DECchip 21264CB Alpha Processor (EV68).

Documentation consulted:

Definition at line 243 of file AlphaCPU.h.


TB

Translation Buffer related functions

int virt2phys (u64 virt, u64 *phys, int flags, bool *asm_bit, u32 instruction)
 Translate a virtual address to a physical address.
int FindTBEntry (u64 virt, int flags)
 Find translation-buffer entry.
void add_tb (u64 virt, u64 pte_phys, u64 pte_flags, int flags)
 Add translation-buffer entry.
void add_tb_i (u64 virt, u64 pte)
 Add translation-buffer entry to the ITB.
void add_tb_d (u64 virt, u64 pte)
 Add translation-buffer entry to the DTB.
void tbia (int flags)
 Invalidate all translation-buffer entries.
void tbiap (int flags)
 Invalidate all process-specific translation-buffer entries.
void tbis (u64 virt, int flags)
 Invalidate single translation-buffer entry.

Public Member Functions

void flush_icache_asm ()
 Empty the instruction cache of lines with the ASM bit clear.
virtual int SaveState (FILE *f)
 Save state to a Virtual Machine State file.
virtual int RestoreState (FILE *f)
 Restore state from a Virtual Machine State file.
void irq_h (int number, bool assert, int delay)
 Assert or release an external interrupt line to the cpu.
int get_cpuid ()
 Return processor number.
void flush_icache ()
 Empty the instruction cache.
virtual void run ()
void execute ()
 Called each clock-cycle.
void release_threads ()
void set_PAL_BASE (u64 pb)
 Set the PALcode BASE register, and determine whether we're running VMS PALcode.
virtual void check_state ()
 Check if threads are still running.
 CAlphaCPU (CConfigurator *cfg, CSystem *system)
 Constructor.
virtual ~CAlphaCPU ()
 Destructor.
u64 get_r (int i, bool translate)
 Get a register value.
u64 get_f (int i)
 Get a fp register value.
void set_r (int reg, u64 val)
 Set a register value.
void set_f (int reg, u64 val)
 Set a fp register value.
u64 get_prbr (void)
 Get the processor base register.
u64 get_hwpcb (void)
 Get the hardware process control block address.
u64 get_pc ()
 Return program counter value.
u64 get_pal_base ()
 Get the PALcode base register.
void enable_icache ()
 Enable i-cache regardles of config file.
void restore_icache ()
 Enable or disable i-cache depending on config file.
u64 get_current_pc_physical ()
 Return the physical address the program counter refers to.
u64 get_instruction_count ()
u32 get_last_instruction ()
 Return the last instruction executed.
u64 get_clean_pc ()
 Return program counter value without PALmode bit.
void next_pc ()
 Jump to next instruction.
void set_pc (u64 p_pc)
 Set program counter to a certain value.
void add_pc (u64 a_pc)
 Add value to the program counter.
u64 get_speed ()
u64 va_form (u64 address, bool bIBOX)
 Convert a virtual address to va_form format.
void listing (u64 from, u64 to)
 Produce disassembly-listing without marker.
void listing (u64 from, u64 to, u64 mark)
 Produce disassembly-listing with marker.
virtual void init ()
 Initialize the CPU.
virtual void start_threads ()
virtual void stop_threads ()

Private Member Functions

int get_icache (u64 address, u32 *data)
 Get an instruction from the instruction cache.
IEEE_fp_load_store
IEEE floating point load and store functions.

u64 ieee_lds (u32 op)
 Convert an IEEE S-floating from memory format to register format.
u32 ieee_sts (u64 op)
 Convert an IEEE S-floating from register format to memory format.
IEEE_fp_conversion
IEEE floating point conversion routines

u64 ieee_cvtst (u64 op, u32 ins)
 Convert an IEEE S-floating to an IEEE T-floating.
u64 ieee_cvtts (u64 op, u32 ins)
 Convert an IEEE T-floating to an IEEE S-floating.
IEEE_fp_operations
IEEE floating point operations

s32 ieee_fcmp (u64 s1, u64 s2, u32 ins, u32 trap_nan)
 Compare 2 IEEE floating-point values.
u64 ieee_cvtif (u64 val, u32 ins, u32 dp)
 Convert 64-bit signed integer to IEEE floating-point value.
u64 ieee_cvtfi (u64 op, u32 ins)
 Convert IEEE floating-point value to 64-bit signed integer.
u64 ieee_fadd (u64 s1, u64 s2, u32 ins, u32 dp, bool sub)
 Add or subtract 2 IEEE floating-point values.
u64 ieee_fmul (u64 s1, u64 s2, u32 ins, u32 dp)
 Multiply 2 IEEE floating-point values.
u64 ieee_fdiv (u64 s1, u64 s2, u32 ins, u32 dp)
 Divide 2 IEEE floating-point values.
u64 ieee_sqrt (u64 op, u32 ins, u32 dp)
 Determine principal square root of a IEEE floating-point value.
IEEE_fp_support
IEEE floating point support functions

int ieee_unpack (u64 op, UFP *r, u32 ins)
 Unpack IEEE floating-point value.
void ieee_norm (UFP *r)
 Normalize IEEE floating-point value.
u64 ieee_rpack (UFP *r, u32 ins, u32 dp)
 Round and pack IEEE floating-point value.
void ieee_trap (u64 trap, u32 instenb, u64 fpcrdsb, u32 ins)
 Set IEEE floating-point trap.
VAX_fp_load_store
VAX floating point load and store functions

u64 vax_ldf (u32 op)
 Convert the VAX F-floating memory format to the VAX floating register format.
u64 vax_ldg (u64 op)
 Convert the VAX G-floating memory format to the VAX floating register format.
u32 vax_stf (u64 op)
 Convert the VAX floating register format to the VAX F-floating memory format.
u64 vax_stg (u64 op)
 Convert the VAX floating register format to the VAX G-floating memory format.
VAX_fp_support
VAX floating point support functions

void vax_trap (u64 mask, u32 ins)
 Set VAX floating-point trap.
void vax_unpack (u64 op, UFP *r, u32 ins)
 Unpack VAX floating-point value.
void vax_unpack_d (u64 op, UFP *r, u32 ins)
 Unpack VAX D-floating-point value.
void vax_norm (UFP *r)
 Normalize VAX floating-point value.
u64 vax_rpack (UFP *r, u32 ins, u32 dp)
 Round and pack VAX floating-point value.
u64 vax_rpack_d (UFP *r, u32 ins)
 Round and pack VAX D-floating-point value.
VAX_fp_operations
VAX floating point operations

int vax_fcmp (u64 s1, u64 s2, u32 ins)
 Compare 2 VAX floating-point values.
u64 vax_cvtif (u64 val, u32 ins, u32 dp)
 Convert 64-bit signed integer to VAX floating-point value.
u64 vax_cvtfi (u64 op, u32 ins)
 Convert VAX floating-point value to 64-bit signed integer.
u64 vax_fadd (u64 s1, u64 s2, u32 ins, u32 dp, bool sub)
 Add or subtract 2 VAX floating-point values.
u64 vax_fmul (u64 s1, u64 s2, u32 ins, u32 dp)
 Multiply 2 VAX floating-point values.
u64 vax_fdiv (u64 s1, u64 s2, u32 ins, u32 dp)
 Divide 2 VAX floating-point values.
u64 vax_sqrt (u64 op, u32 ins, u32 dp)
 Determine principal square root of a VAX floating-point value.
VMS_pal_call
VMS PALcode CALL replacement routines.

void vmspal_call_cflush ()
 Implementation of CALL_PAL CFLUSH opcode.
void vmspal_call_draina ()
 Implementation of CALL_PAL DRAINA opcode.
void vmspal_call_ldqp ()
 Implementation of CALL_PAL LDQP opcode.
void vmspal_call_stqp ()
 Implementation of CALL_PAL STQP opcode.
void vmspal_call_swpctx ()
 Implementation of CALL_PAL SWPCTX opcode.
void vmspal_call_mfpr_asn ()
 Implementation of CALL_PAL MFPR_ASN opcode.
void vmspal_call_mtpr_asten ()
 Implementation of CALL_PAL MTPR_ASTEN opcode.
void vmspal_call_mtpr_astsr ()
 Implementation of CALL_PAL MTPR_ASTSR opcode.
void vmspal_call_cserve ()
 Implementation of CALL_PAL CSERVE opcode.
void vmspal_call_mfpr_fen ()
 Implementation of CALL_PAL MFPR_FEN opcode.
void vmspal_call_mtpr_fen ()
 Implementation of CALL_PAL MTPR_FEN opcode.
void vmspal_call_mfpr_ipl ()
 Implementation of CALL_PAL MFPR_IPL opcode.
void vmspal_call_mtpr_ipl ()
 Implementation of CALL_PAL MTPR_IPL opcode.
void vmspal_call_mfpr_mces ()
 Implementation of CALL_PAL MFPR_MCES opcode.
void vmspal_call_mtpr_mces ()
 Implementation of CALL_PAL MTPR_MCES opcode.
void vmspal_call_mfpr_pcbb ()
 Implementation of CALL_PAL MFPR_PCBB opcode.
void vmspal_call_mfpr_prbr ()
 Implementation of CALL_PAL MFPR_PRBR opcode.
void vmspal_call_mtpr_prbr ()
 Implementation of CALL_PAL MTPR_PRBR opcode.
void vmspal_call_mfpr_ptbr ()
 Implementation of CALL_PAL MFPR_PTBR opcode.
void vmspal_call_mfpr_scbb ()
 Implementation of CALL_PAL MFPR_SCBB opcode.
void vmspal_call_mtpr_scbb ()
 Implementation of CALL_PAL MTPR_SCBB opcode.
void vmspal_call_mtpr_sirr ()
 Implementation of CALL_PAL MTPR_SIRR opcode.
void vmspal_call_mfpr_sisr ()
 Implementation of CALL_PAL MFPR_SISR opcode.
void vmspal_call_mfpr_tbchk ()
 Implementation of CALL_PAL MFPR_TBCHK opcode.
void vmspal_call_mtpr_tbia ()
 Implementation of CALL_PAL MTPR_TBIA opcode.
void vmspal_call_mtpr_tbiap ()
 Implementation of CALL_PAL MTPR_TBIAP opcode.
void vmspal_call_mtpr_tbis ()
 Implementation of CALL_PAL MTPR_TBIS opcode.
void vmspal_call_mfpr_esp ()
 Implementation of CALL_PAL MFPR_ESP opcode.
void vmspal_call_mtpr_esp ()
 Implementation of CALL_PAL MTPR_ESP opcode.
void vmspal_call_mfpr_ssp ()
 Implementation of CALL_PAL MFPR_SSP opcode.
void vmspal_call_mtpr_ssp ()
 Implementation of CALL_PAL MTPR_SSP opcode.
void vmspal_call_mfpr_usp ()
 Implementation of CALL_PAL MFPR_USP opcode.
void vmspal_call_mtpr_usp ()
 Implementation of CALL_PAL MTPR_USP opcode.
void vmspal_call_mtpr_tbisd ()
 Implementation of CALL_PAL MTPR_TBISD opcode.
void vmspal_call_mtpr_tbisi ()
 Implementation of CALL_PAL MTPR_TBISI opcode.
void vmspal_call_mfpr_asten ()
 Implementation of CALL_PAL MFPR_ASTEN opcode.
void vmspal_call_mfpr_astsr ()
 Implementation of CALL_PAL MFPR_ASTSR opcode.
void vmspal_call_mfpr_vptb ()
 Implementation of CALL_PAL MFPR_VPTB opcode.
void vmspal_call_mtpr_datfx ()
 Implementation of CALL_PAL MTPR_DATFX opcode.
void vmspal_call_mfpr_whami ()
 Implementation of CALL_PAL MFPR_WHAMI opcode.
void vmspal_call_imb ()
 Implementation of CALL_PAL IMB opcode.
void vmspal_call_prober ()
 Implementation of CALL_PAL PROBER opcode.
void vmspal_call_probew ()
 Implementation of CALL_PAL PROBEW opcode.
void vmspal_call_rd_ps ()
 Implementation of CALL_PAL RD_PS opcode.
int vmspal_call_rei ()
 Implementation of CALL_PAL REI opcode.
void vmspal_call_swasten ()
 Implementation of CALL_PAL SWASTEN opcode.
void vmspal_call_wr_ps_sw ()
 Implementation of CALL_PAL WR_PS_SW opcode.
void vmspal_call_rscc ()
 Implementation of CALL_PAL RSCC opcode.
void vmspal_call_read_unq ()
 Implementation of CALL_PAL READ_UNQ opcode.
void vmspal_call_write_unq ()
 Implementation of CALL_PAL WRITE_UNQ opcode.
VMS_pal_ent
VMS PALcode replacement trap/exception entry-points.

int vmspal_ent_dtbm_double_3 (int flags)
 Entry point for Double Data Translation Buffer Miss.
int vmspal_ent_dtbm_single (int flags)
 Entry point for Single Data Translation Buffer Miss.
int vmspal_ent_itbm (int flags)
 Entry point for Instruction Translation Buffer Miss.
int vmspal_ent_iacv (int flags)
 Entry point for IStream Access Violation.
int vmspal_ent_dfault (int flags)
 Entry point for DStream Fault.
int vmspal_ent_ext_int (int ei)
 Interrupt entry point for External Interrupts.
int vmspal_ent_sw_int (int si)
 Interrupt entry point for Software Interrupts.
int vmspal_ent_ast_int (int ast)
 Interrupt entry point for Asynchronous System Traps.
VMS_pal_int
Internal routines used by VMS PALcode replacement.

int vmspal_int_initiate_exception ()
 Pass control to the OS for handling the exception.
int vmspal_int_initiate_interrupt ()
 Pass control to the OS for handling the interrupt.

Private Attributes

Poco::ThreadmyThread
Poco::Semaphore mySemaphore
bool StopThread
bool icache_enabled
u64 cc_large
u64 start_icount
u64 start_cc
Poco::Timestamp start_time
u64 prev_icount
u64 prev_cc
u64 prev_time
u64 cc_per_instruction
u64 ins_per_timer_int
u64 next_timer_int
u64 cpu_hz
struct CAlphaCPU::SCPU_state state
 Determines CPU state that needs to be saved to the state file.
u64 current_pc_physical
 Physical address of current instruction.
u32 last_instruction

Data Structures

struct  SCPU_state
 The state structure contains all elements that need to be saved to the statefile. More...

Constructor & Destructor Documentation

CAlphaCPU::CAlphaCPU ( CConfigurator cfg,
CSystem system 
)

Constructor.

Definition at line 372 of file AlphaCPU.cpp.

CAlphaCPU::~CAlphaCPU (  )  [virtual]

Destructor.

Definition at line 455 of file AlphaCPU.cpp.

References stop_threads().


Member Function Documentation

void CAlphaCPU::flush_icache_asm (  )  [inline]

Empty the instruction cache of lines with the ASM bit clear.

Definition at line 568 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::SICache::asm_bit, CAlphaCPU::SCPU_state::icache, icache_enabled, ICACHE_ENTRIES, state, and CAlphaCPU::SCPU_state::SICache::valid.

Referenced by vmspal_call_mtpr_tbiap().

int CAlphaCPU::SaveState ( FILE *  f  )  [virtual]

Save state to a Virtual Machine State file.

Implements CSystemComponent.

Definition at line 1342 of file AlphaCPU.cpp.

References cpu_magic1, cpu_magic2, CSystemComponent::devid_string, and state.

int CAlphaCPU::RestoreState ( FILE *  f  )  [virtual]

Restore state from a Virtual Machine State file.

Implements CSystemComponent.

Definition at line 1357 of file AlphaCPU.cpp.

References cpu_magic1, cpu_magic2, CSystemComponent::devid_string, and state.

void CAlphaCPU::irq_h ( int  number,
bool  assert,
int  delay 
) [inline]

int CAlphaCPU::get_cpuid (  )  [inline]

Return processor number.

Definition at line 727 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::iProcNum, and state.

Referenced by CSystem::cchip_csr_write(), get_hwpcb(), get_prbr(), CTraceEngine::trace(), and CTraceEngine::trace_br().

void CAlphaCPU::flush_icache (  )  [inline]

void CAlphaCPU::run ( void   )  [virtual]

void CAlphaCPU::execute (  ) 

Called each clock-cycle.

This is where the actual CPU emulation takes place. Each clocktick, one instruction is processed by the processor. The instruction pipeline is not emulated, things are complicated enough as it is. The one exception is the instruction cache, which is implemented, to accomodate self-modifying code. The instruction cache can be disabled if self-modifying code is not expected.

Definition at line 553 of file AlphaCPU.cpp.

References CAlphaCPU::SCPU_state::asten, CAlphaCPU::SCPU_state::aster, CAlphaCPU::SCPU_state::astrr, CAlphaCPU::SCPU_state::cc, CAlphaCPU::SCPU_state::cc_ena, cc_large, cc_per_instruction, CAlphaCPU::SCPU_state::check_int, CAlphaCPU::SCPU_state::check_timers, CAlphaCPU::SCPU_state::cm, CSystemComponent::cSystem, CAlphaCPU::SCPU_state::current_pc, dbg_string, dbg_strptr, DO_ACTION, CAlphaCPU::SCPU_state::eien, CAlphaCPU::SCPU_state::eir, CAlphaCPU::SCPU_state::f, get_icache(), GO_PAL, ins_per_timer_int, CAlphaCPU::SCPU_state::instruction_count, INTERRUPT, CSystem::interrupt(), CAlphaCPU::SCPU_state::irq_h_timer, last_instruction, MT_FPCR, next_pc(), next_timer_int, NOP, OP, CAlphaCPU::SCPU_state::pc, CAlphaCPU::SCPU_state::r, RC, CSystem::ReadMem(), CAlphaCPU::SCPU_state::sien, CAlphaCPU::SCPU_state::sir, state, U64, UNKNOWN1, and UNKNOWN2.

Referenced by listing(), and run().

void CAlphaCPU::release_threads (  ) 

Definition at line 343 of file AlphaCPU.cpp.

References mySemaphore, and Poco::Semaphore::set().

void CAlphaCPU::set_PAL_BASE ( u64  pb  )  [inline]

Set the PALcode BASE register, and determine whether we're running VMS PALcode.

Definition at line 582 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::pal_base, CAlphaCPU::SCPU_state::pal_vms, state, and U64.

Referenced by CSystem::LoadROM().

void CAlphaCPU::check_state (  )  [virtual]

Check if threads are still running.

Calibrate the CPU timing loop.

Reimplemented from CSystemComponent.

Definition at line 503 of file AlphaCPU.cpp.

References cc_large, cc_per_instruction, cpu_hz, Poco::Timestamp::elapsed(), FAILURE, CAlphaCPU::SCPU_state::instruction_count, Poco::Thread::isRunning(), myThread, prev_cc, prev_icount, prev_time, start_time, and state.

u64 CAlphaCPU::get_r ( int  i,
bool  translate 
) [inline]

Get a register value.

If translate is true, use shadow registers if currently enabled.

Definition at line 828 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::r, RREG, and state.

Referenced by CSystem::panic(), CTraceEngine::parse(), CTraceEngine::trace(), and CTraceEngine::write_arglist().

u64 CAlphaCPU::get_f ( int  i  )  [inline]

Get a fp register value.

Definition at line 839 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::f, and state.

Referenced by CSystem::panic(), and CTraceEngine::parse().

void CAlphaCPU::set_r ( int  reg,
u64  val 
) [inline]

Set a register value.

Definition at line 847 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::r, and state.

Referenced by CTraceEngine::parse().

void CAlphaCPU::set_f ( int  reg,
u64  val 
) [inline]

Set a fp register value.

Definition at line 855 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::f, and state.

Referenced by CTraceEngine::parse().

u64 CAlphaCPU::get_prbr ( void   )  [inline]

u64 CAlphaCPU::get_hwpcb ( void   )  [inline]

u64 CAlphaCPU::get_pc (  )  [inline]

Return program counter value.

Definition at line 771 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::pc, and state.

Referenced by CSystem::cchip_csr_write(), CSystem::panic(), CTraceEngine::parse(), and CTraceEngine::run_script().

u64 CAlphaCPU::get_pal_base (  )  [inline]

Get the PALcode base register.

Definition at line 863 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::pal_base, and state.

void CAlphaCPU::enable_icache (  ) 

Enable i-cache regardles of config file.

Required for SRM-ROM decompression.

Definition at line 2060 of file AlphaCPU.cpp.

References icache_enabled.

Referenced by CSystem::LoadROM().

void CAlphaCPU::restore_icache (  ) 

Enable or disable i-cache depending on config file.

Definition at line 2068 of file AlphaCPU.cpp.

References flush_icache(), CConfigurator::get_bool_value(), icache_enabled, and CSystemComponent::myCfg.

Referenced by CSystem::LoadROM().

u64 CAlphaCPU::get_current_pc_physical (  )  [inline]

Return the physical address the program counter refers to.

Definition at line 781 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::pc_phys, and state.

Referenced by CSystem::panic(), and CTraceEngine::parse().

u64 CAlphaCPU::get_instruction_count (  ) 

Definition at line 1331 of file AlphaCPU.cpp.

References CAlphaCPU::SCPU_state::instruction_count, and state.

Referenced by CSystem::panic(), and CTraceEngine::parse().

u32 CAlphaCPU::get_last_instruction ( void   )  [inline]

Return the last instruction executed.

Definition at line 913 of file AlphaCPU.h.

References last_instruction.

Referenced by CTraceEngine::parse().

u64 CAlphaCPU::get_clean_pc (  )  [inline]

Return program counter value without PALmode bit.

Definition at line 790 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::pc, state, and U64.

Referenced by CTraceEngine::parse(), and CTraceEngine::run_script().

void CAlphaCPU::next_pc (  )  [inline]

Jump to next instruction.

Definition at line 798 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::pc, CAlphaCPU::SCPU_state::pc_phys, CAlphaCPU::SCPU_state::rem_ins_in_page, and state.

Referenced by execute().

void CAlphaCPU::set_pc ( u64  p_pc  )  [inline]

void CAlphaCPU::add_pc ( u64  a_pc  )  [inline]

Add value to the program counter.

Definition at line 818 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::pc, CAlphaCPU::SCPU_state::rem_ins_in_page, and state.

u64 CAlphaCPU::get_speed (  )  [inline]

Definition at line 283 of file AlphaCPU.h.

References cpu_hz.

Referenced by CDPR::init().

u64 CAlphaCPU::va_form ( u64  address,
bool  bIBOX 
) [inline]

Convert a virtual address to va_form format.

Used for IPR VA_FORM [HRM 5-5..6] and IPR IVA_FORM [HRM 5-9].

Definition at line 705 of file AlphaCPU.h.

References CAlphaCPU::SCPU_state::i_ctl_va_mode, CAlphaCPU::SCPU_state::i_ctl_vptb, state, U64, CAlphaCPU::SCPU_state::va_ctl_va_mode, and CAlphaCPU::SCPU_state::va_ctl_vptb.

Referenced by vmspal_ent_dtbm_single(), and vmspal_ent_itbm().

void CAlphaCPU::listing ( u64  from,
u64  to 
)

Produce disassembly-listing without marker.

Parameters:
from Address of first instruction to be disassembled.
to Address of instruction following the last instruction to be disassembled.

Definition at line 1296 of file AlphaCPU.cpp.

Referenced by CTraceEngine::list_all(), CSystem::panic(), and CTraceEngine::parse().

void CAlphaCPU::listing ( u64  from,
u64  to,
u64  mark 
)

Produce disassembly-listing with marker.

Parameters:
from Address of first instruction to be disassembled.
to Address of instruction following the last instruction to be disassembled.
mark Address of instruction to be underlined with a marker line.

Definition at line 1309 of file AlphaCPU.cpp.

References bDisassemble, bListing, execute(), LL, CAlphaCPU::SCPU_state::pc, and state.

int CAlphaCPU::virt2phys ( u64  virt,
u64 phys,
int  flags,
bool *  asm_bit,
u32  ins 
)

Translate a virtual address to a physical address.

Translate a 64-bit virtual address into a 64-bit physical address, using the page table buffers.

The following steps are taken to resolve the address:

  • See if the address can be found in the translation buffer.
  • If not, try to load the right page table entry into the translation buffer, if this is not possible, trap to the OS.
  • Check access privileges.
  • Check fault bits.
Parameters:
virt Virtual address to be translated.
phys Pointer to where the physical address is to be returned.
flags Set of flags that determine the exact functioning of the function. A combination of the following flags:
  • ACCESS_READ Data-read-access.
  • ACCESS_WRITE Data-write-access.
  • ACCESS_EXEC Code-read-access.
  • NO_CHECK Do not perform access checks.
  • VPTE VPTE access; if this misses, it's a double miss.
  • FAKE Access is not initiated by executing code, but by the debugger. If a translation can't be found through the translation buffer, don't bother.
  • ALT Use alt_cm for access checks instead of cm.
  • RECUR Recursive try. We tried to find this address before, added a TB entry, and now it should sail through.
  • PROBE Access is for a PROBER or PROBEW access; Don't swap in the page if it is outswapped.
  • PROBEW Access is for a PROBEW access.
asm_bit Status of the ASM (address space match) bit in the page-table-entry.
ins Instruction currently being executed. Important for the correct handling of traps.
Returns:
0 on success, -1 if address could not be converted without help (in this case state.pc contains the address of the next instruction to execute (PALcode or OS entry point).

Definition at line 1505 of file AlphaCPU.cpp.

References CAlphaCPU::SCPU_state::STBEntry::access, ACCESS_EXEC, ACCESS_MODE, ACCESS_WRITE, ALT, CAlphaCPU::SCPU_state::alt_cm, CAlphaCPU::SCPU_state::STBEntry::asm_bit, CAlphaCPU::SCPU_state::asn, CAlphaCPU::SCPU_state::asn0, bListing, bTB_Debug, CAlphaCPU::SCPU_state::cm, CAlphaCPU::SCPU_state::current_pc, DFAULT, DTBM_DOUBLE_3, DTBM_SINGLE, CAlphaCPU::SCPU_state::exc_addr, CAlphaCPU::SCPU_state::exc_sum, FAKE, CAlphaCPU::SCPU_state::STBEntry::fault, CAlphaCPU::SCPU_state::fault_va, FindTBEntry(), CAlphaCPU::SCPU_state::i_ctl_spe, I_GETOP, IACV, ITB_MISS, CAlphaCPU::SCPU_state::STBEntry::keep_mask, LL, CAlphaCPU::SCPU_state::m_ctl_spe, CAlphaCPU::SCPU_state::mm_stat, NO_CHECK, CAlphaCPU::SCPU_state::pal_base, CAlphaCPU::SCPU_state::pal_vms, CAlphaCPU::SCPU_state::STBEntry::phys, RECUR, REG_1, set_pc(), SPE_0_MAP, SPE_0_MASK, SPE_0_MATCH, SPE_1_ADD, SPE_1_MAP, SPE_1_MASK, SPE_1_MATCH, SPE_1_TEST, SPE_2_MAP, SPE_2_MASK, SPE_2_MATCH, state, CAlphaCPU::SCPU_state::tb, vmspal_ent_dfault(), vmspal_ent_dtbm_double_3(), vmspal_ent_dtbm_single(), vmspal_ent_iacv(), vmspal_ent_itbm(), and VPTE.

Referenced by get_hwpcb(), get_icache(), get_prbr(), real_address(), vmspal_call_prober(), vmspal_call_probew(), vmspal_ent_dtbm_single(), and vmspal_ent_itbm().

void CAlphaCPU::init (  )  [virtual]

void CAlphaCPU::start_threads (  )  [virtual]

void CAlphaCPU::stop_threads (  )  [virtual]

int CAlphaCPU::get_icache ( u64  address,
u32 data 
) [inline, private]

Get an instruction from the instruction cache.

If necessary, fill a new cache block from memory.

get_icache checks all cache entries, to see if there is a cache entry that matches the current address space number, and that contains the address we're looking for. If it exists, the instruction is fetched from this cache, otherwise, the physical address for the instruction is calculated, and the cache block is filled.

The last cache entry that was a hit is remembered, so that cache entry is checked first on the next instruction. (very likely to be the same cache block)

It would be easiest to do without the instruction cache altogether, but unfortunately SRM uses self-modifying code, that relies on the correct instruction stream to remain in the cache.

Definition at line 608 of file AlphaCPU.h.

References ACCESS_EXEC, CAlphaCPU::SCPU_state::SICache::address, CAlphaCPU::SCPU_state::SICache::asm_bit, CAlphaCPU::SCPU_state::asn, CAlphaCPU::SCPU_state::SICache::asn, CSystemComponent::cSystem, current_pc_physical, CAlphaCPU::SCPU_state::SICache::data, endian_32, CAlphaCPU::SCPU_state::icache, ICACHE_BYTE_MASK, icache_enabled, ICACHE_ENTRIES, ICACHE_INDEX_MASK, ICACHE_LINE_SIZE, ICACHE_MATCH_MASK, CAlphaCPU::SCPU_state::last_found_icache, CAlphaCPU::SCPU_state::next_icache, CAlphaCPU::SCPU_state::SICache::p_address, CAlphaCPU::SCPU_state::pc_phys, CSystem::PtrToMem(), CSystem::ReadMem(), CAlphaCPU::SCPU_state::rem_ins_in_page, state, U64, CAlphaCPU::SCPU_state::SICache::valid, and virt2phys().

Referenced by execute().

int CAlphaCPU::FindTBEntry ( u64  virt,
int  flags 
) [private]

Find translation-buffer entry.

Try to find a translation-buffer entry that maps the page inside which the specified virtual address lies.

Parameters:
virt Virtual address to find in translation buffer.
flags ACCESS_EXEC determines which translation buffer to use.
Returns:
Number of matching entry, or -1 if no match found.

Definition at line 1433 of file AlphaCPU.cpp.

References ACCESS_EXEC, ACCESS_WRITE, CAlphaCPU::SCPU_state::STBEntry::asm_bit, CAlphaCPU::SCPU_state::STBEntry::asn, CAlphaCPU::SCPU_state::asn, CAlphaCPU::SCPU_state::asn0, CAlphaCPU::SCPU_state::last_found_tb, CAlphaCPU::SCPU_state::STBEntry::match_mask, state, CAlphaCPU::SCPU_state::tb, TB_ENTRIES, CAlphaCPU::SCPU_state::STBEntry::valid, and CAlphaCPU::SCPU_state::STBEntry::virt.

Referenced by add_tb(), tbis(), and virt2phys().

void CAlphaCPU::add_tb ( u64  virt,
u64  pte_phys,
u64  pte_flags,
int  flags 
) [private]

void CAlphaCPU::add_tb_i ( u64  virt,
u64  pte 
) [private]

Add translation-buffer entry to the ITB.

The format of the PTE field is:

   63              44 43           13 12  11  10  9   8  7 6  5  4  3   0
  +------------------+---------------+--+---+---+---+---+-+----+---+-----+
  |                  |  PA <43:13>   |  |URE|SRE|ERE|KRE| | GH |ASM|     |
  +------------------+---------------+--+---+---+---+---+-+----+---+-----+
                                        +---------------+    |   |   
                                                    |        |   |       
  (user,supervisor,executive,kernel)read enable ----+        |   |       
                                       granularity hint -----+   |       
                                        address space match -----+       

Parameters:
virt Virtual address.
pte Translation in ITB_PTE format.

Definition at line 1999 of file AlphaCPU.cpp.

References ACCESS_EXEC, and add_tb().

Referenced by vmspal_ent_itbm().

void CAlphaCPU::add_tb_d ( u64  virt,
u64  pte 
) [private]

Add translation-buffer entry to the DTB.

The format of the PTE field is:

   63 62           32 31     16  15  14  13  12  11  10  9   8  7 6  5  4  3  2   1  0
  +--+---------------+---------+---+---+---+---+---+---+---+---+-+----+---+-+---+---+-+
  |  |  PA <43:13>   |         |UWE|SWE|EWE|KWE|URE|SRE|ERE|KRE| | GH |ASM| |FOW|FOR| |
  +--+---------------+---------+---+---+---+---+---+---+---+---+-+----+---+-+---+---+-+
                               +-------------------------------+    |   |   +-------+
                                                           |        |   |       |
  (user,supervisor,executive,kernel)(read,write)enable ----+        |   |       |
                                              granularity hint -----+   |       |
                                               address space match -----+       |
                                                      fault-on-(read,write) ----+

Parameters:
virt Virtual address.
pte Translation in DTB_PTE format.

Definition at line 1974 of file AlphaCPU.cpp.

References ACCESS_READ, and add_tb().

Referenced by vmspal_ent_dtbm_double_3(), and vmspal_ent_dtbm_single().

void CAlphaCPU::tbia ( int  flags  )  [private]

Invalidate all translation-buffer entries.

Invalidate all translation-buffer entries in one of the translation buffers.

Parameters:
flags ACCESS_EXEC determines which translation buffer to use.

Definition at line 2011 of file AlphaCPU.cpp.

References ACCESS_EXEC, CAlphaCPU::SCPU_state::last_found_tb, CAlphaCPU::SCPU_state::next_tb, state, CAlphaCPU::SCPU_state::tb, TB_ENTRIES, and CAlphaCPU::SCPU_state::STBEntry::valid.

Referenced by init(), and vmspal_call_mtpr_tbia().

void CAlphaCPU::tbiap ( int  flags  )  [private]

Invalidate all process-specific translation-buffer entries.

Invalidate all translation-buffer entries that do not have the ASM bit set in one of the translation buffers.

Parameters:
flags ACCESS_EXEC determines which translation buffer to use.

Definition at line 2030 of file AlphaCPU.cpp.

References ACCESS_EXEC, CAlphaCPU::SCPU_state::STBEntry::asm_bit, state, CAlphaCPU::SCPU_state::tb, TB_ENTRIES, and CAlphaCPU::SCPU_state::STBEntry::valid.

Referenced by vmspal_call_mtpr_tbiap().

void CAlphaCPU::tbis ( u64  virt,
int  flags 
) [private]

Invalidate single translation-buffer entry.

Parameters:
virt Virtual address for which the entry should be invalidated.
flags ACCESS_EXEC determines which translation buffer to use.

Definition at line 2045 of file AlphaCPU.cpp.

References ACCESS_EXEC, FindTBEntry(), state, CAlphaCPU::SCPU_state::tb, and CAlphaCPU::SCPU_state::STBEntry::valid.

Referenced by vmspal_call_mtpr_tbis(), vmspal_call_mtpr_tbisd(), vmspal_call_mtpr_tbisi(), and vmspal_ent_dfault().

u64 CAlphaCPU::ieee_lds ( u32  op  )  [private]

Convert an IEEE S-floating from memory format to register format.

Adjust the exponent base, and widen the exponent and fraction fields.

Parameters:
op IEEE S-floating value in memory format.
Returns:
IEEE S-floating value in register format.

Definition at line 179 of file AlphaCPU_ieeefloat.cpp.

References FPR_NAN, FPR_SIGN, FPR_V_EXP, S_BIAS, S_EXP, S_GETEXP, S_NAN, S_SIGN, S_V_FRAC, and T_BIAS.

u32 CAlphaCPU::ieee_sts ( u64  op  )  [private]

Convert an IEEE S-floating from register format to memory format.

Adjust the exponent base, and make the exponent and fraction fields smaller.

Parameters:
op IEEE S-floating value in register format.
Returns:
IEEE S-floating value in memory format.

Definition at line 199 of file AlphaCPU_ieeefloat.cpp.

References FPR_GETEXP, FPR_GETSIGN, FPR_NAN, S_BIAS, S_EXP, S_NAN, S_SIGN, S_V_EXP, S_V_FRAC, T_BIAS, and X64_LONG.

u64 CAlphaCPU::ieee_cvtst ( u64  op,
u32  ins 
) [private]

Convert an IEEE S-floating to an IEEE T-floating.

LDS doesn't handle denorms correctly.

Parameters:
op IEEE S-floating value.
ins The instruction currently being executed. Used to properly handle exceptions.
Returns:
IEEE T-floating value.

Definition at line 235 of file AlphaCPU_ieeefloat.cpp.

References DT_T, ufp::exp, ieee_rpack(), ieee_unpack(), S_BIAS, T_BIAS, and UFT_DENORM.

u64 CAlphaCPU::ieee_cvtts ( u64  op,
u32  ins 
) [private]

Convert an IEEE T-floating to an IEEE S-floating.

Parameters:
op IEEE T-floating value.
ins The instruction currently being executed. Used to properly handle exceptions and to determine the rounding mode.
Returns:
IEEE S-floating.

Definition at line 260 of file AlphaCPU_ieeefloat.cpp.

References DT_S, ieee_rpack(), ieee_unpack(), Q_FINITE, QNAN, UFT_INF, and UFT_NAN.

s32 CAlphaCPU::ieee_fcmp ( u64  s1,
u64  s2,
u32  ins,
u32  trap_nan 
) [private]

Compare 2 IEEE floating-point values.

The following steps are taken:

  • Take care of NaNs
  • Force -0 to +0
  • Then normal compare will work (even on inf and denorms)
Parameters:
s1 First IEEE floating to be compared.
s1 Second IEEE floating to be compared.
ins The instruction currently being executed. Used to properly handle exceptions.
Returns:
0 if s1==s2, 1 if s1>s2, -1 if s1<s2.

Definition at line 301 of file AlphaCPU_ieeefloat.cpp.

References ufp::exp, FPCR_INVD, ufp::frac, ieee_trap(), ieee_unpack(), ufp::sign, TRAP_INV, UFT_NAN, and UFT_ZERO.

u64 CAlphaCPU::ieee_cvtif ( u64  val,
u32  ins,
u32  dp 
) [private]

Convert 64-bit signed integer to IEEE floating-point value.

Parameters:
val 64-bit signed integer to be converted.
ins The instruction currently being executed. Used to properly handle exceptions and to determine the rounding mode.
dp DT_S for S-floating or DT_T for T-floating.
Returns:
IEEE floating.

Definition at line 340 of file AlphaCPU_ieeefloat.cpp.

References ufp::exp, ufp::frac, ieee_norm(), ieee_rpack(), NEG_Q, ufp::sign, and T_BIAS.

u64 CAlphaCPU::ieee_cvtfi ( u64  op,
u32  ins 
) [private]

Convert IEEE floating-point value to 64-bit signed integer.

Rounding code from SoftFloat.

The Alpha architecture specifies return of the low order bits of the true result, whereas the IEEE standard specifies the return of the maximum plus or minus value

Parameters:
op IEEE floating to be converted.
ins The instruction currently being executed. Used to properly handle exceptions.
Returns:
64-bit signed integer.

Definition at line 373 of file AlphaCPU_ieeefloat.cpp.

References ufp::exp, FPCR_INED, FPCR_INVD, ufp::frac, I_FRND_M, I_FRND_N, I_FRND_P, I_FTRP_V, I_GETFRND, ieee_trap(), ieee_unpack(), IMMAX, IPMAX, NEG_Q, Q_FINITE, Q_SIGN, Q_SUI, ufp::sign, T_BIAS, TRAP_INE, TRAP_INV, TRAP_IOV, UF_V_NM, UFT_ZERO, and X64_QUAD.

u64 CAlphaCPU::ieee_fadd ( u64  s1,
u64  s2,
u32  ins,
u32  dp,
bool  sub 
) [private]

Add or subtract 2 IEEE floating-point values.

The following steps are taken:

  • Take care of NaNs and infinites
  • Test for zero (fast exit)
  • Sticky logic for floating add
    • If result normalized, sticky in right place
    • If result carries out, renormalize, retain sticky
  • Sticky logic for floating subtract
    • If shift < guard, no sticky bits; 64b result is exact
    • If shift <= 1, result may require extensive normalization, but there are no sticky bits to worry about
    • If shift >= guard, there is a sticky bit, but normalization is at most 1 place, sticky bit is retained for rounding purposes (but not in low order bit)
Parameters:
s1 Augend or minuend.
s2 Addend or subtrahend.
ins The instruction currently being executed. Used to properly handle exceptions.
dp DT_S for S-floating or DT_T for T-floating.
sub subtract if true, add if false.
Returns:
IEEE floating.

Definition at line 465 of file AlphaCPU_ieeefloat.cpp.

References CQNAN, ufp::exp, FPCR_INVD, FPR_SIGN, ufp::frac, ieee_norm(), ieee_rpack(), ieee_trap(), ieee_unpack(), QNAN, ufp::sign, TRAP_INV, UF_NM, UFT_INF, UFT_NAN, UFT_ZERO, and X64_QUAD.

u64 CAlphaCPU::ieee_fmul ( u64  s1,
u64  s2,
u32  ins,
u32  dp 
) [private]

Multiply 2 IEEE floating-point values.

The following steps are taken:

  • Take care of NaNs and infinites
  • Test for zero operands (fast exit)
  • 64b x 64b fraction multiply, yielding 128b result
  • Normalize (at most 1 bit)
  • Insert "sticky" bit in low order fraction, for rounding
Because IEEE fractions have a range of [1,2), the result can have a range of [1,4). Results in the range of [1,2) appear to be denormalized by one place, when in fact they are correct. Results in the range of [2,4) appear to be in correct, when in fact they are 2X larger. This problem is taken care of in the result exponent calculation.

Parameters:
s1 Multiplicand.
s2 Multiplier.
ins The instruction currently being executed. Used to properly handle exceptions.
dp DT_S for S-floating or DT_T for T-floating.
Returns:
IEEE floating.

Definition at line 563 of file AlphaCPU_ieeefloat.cpp.

References CQNAN, ufp::exp, FMINF, FMZERO, FPCR_INVD, FPINF, FPZERO, ufp::frac, ieee_norm(), ieee_rpack(), ieee_trap(), ieee_unpack(), QNAN, ufp::sign, T_BIAS, TRAP_INV, uemul64(), UFT_INF, UFT_NAN, and UFT_ZERO.

u64 CAlphaCPU::ieee_fdiv ( u64  s1,
u64  s2,
u32  ins,
u32  dp 
) [private]

Divide 2 IEEE floating-point values.

The following steps are taken:

  • Take care of NaNs and infinites
  • Check for zero cases
  • Divide fractions (55b to develop a rounding bit)
  • Set sticky bit if remainder non-zero
Because IEEE fractions have a range of [1,2), the result can have a range of (.5,2). Results in the range of [1,2) are correct. Results in the range of (.5,1) need to be normalized by one place.

Parameters:
s1 Dividend.
s2 Divisor.
ins The instruction currently being executed. Used to properly handle exceptions.
dp DT_S for S-floating or DT_T for T-floating.
Returns:
IEEE floating.

Definition at line 622 of file AlphaCPU_ieeefloat.cpp.

References CQNAN, ufp::exp, FMINF, FMZERO, FPCR_DZED, FPCR_INVD, FPINF, FPZERO, ufp::frac, ieee_norm(), ieee_rpack(), ieee_trap(), ieee_unpack(), QNAN, ufp::sign, T_BIAS, TRAP_DZE, TRAP_INV, ufdiv64(), UFT_INF, UFT_NAN, and UFT_ZERO.

u64 CAlphaCPU::ieee_sqrt ( u64  op,
u32  ins,
u32  dp 
) [private]

Determine principal square root of a IEEE floating-point value.

The following steps are taken:

  • Take care of NaNs, +infinite, zero
  • Check for negative operand
  • Compute result exponent
  • Compute sqrt of fraction
Parameters:
op IEEE floating.
ins The instruction currently being executed. Used to properly handle exceptions.
dp DT_S for S-floating or DT_T for T-floating.
Returns:
IEEE floating.

Definition at line 695 of file AlphaCPU_ieeefloat.cpp.

References CQNAN, ufp::exp, FPCR_INVD, ufp::frac, fsqrt64(), ieee_rpack(), ieee_trap(), ieee_unpack(), QNAN, ufp::sign, T_BIAS, TRAP_INV, UFT_INF, UFT_NAN, and UFT_ZERO.

int CAlphaCPU::ieee_unpack ( u64  op,
UFP r,
u32  ins 
) [private]

Unpack IEEE floating-point value.

Converts a IEEE floating-point value to it's sign, exponent and fraction components.

Parameters:
op IEEE floating.
r Pointer to the unpacked-floating-point UFP structure where the results are to be returned.
ins The instruction currently being executed. Used to properly handle exceptions.
Returns:
Returns the type of value (UFT_ZERO, UFT_FIN, etc.).

Definition at line 740 of file AlphaCPU_ieeefloat.cpp.

References ufp::exp, CAlphaCPU::SCPU_state::fpcr, FPCR_DNZ, FPCR_INVD, FPR_GETEXP, FPR_GETFRAC, FPR_GETSIGN, FPR_GUARD, FPR_HB, FPR_NAN, ufp::frac, ieee_norm(), ieee_trap(), QNAN, ufp::sign, state, TRAP_INV, UFT_DENORM, UFT_FIN, UFT_INF, UFT_NAN, and UFT_ZERO.

Referenced by ieee_cvtfi(), ieee_cvtst(), ieee_cvtts(), ieee_fadd(), ieee_fcmp(), ieee_fdiv(), ieee_fmul(), and ieee_sqrt().

void CAlphaCPU::ieee_norm ( UFP r  )  [private]

Normalize IEEE floating-point value.

Normalize exponent and fraction components. Input must be zero, finite, or denorm.

Parameters:
r Pointer to the unpacked-floating-point UFP structure containing the value to be normalized, and where the results are to be returned.

Definition at line 783 of file AlphaCPU_ieeefloat.cpp.

References ufp::exp, ufp::frac, U64, UF_NM, and X64_QUAD.

Referenced by ieee_cvtif(), ieee_fadd(), ieee_fdiv(), ieee_fmul(), and ieee_unpack().

u64 CAlphaCPU::ieee_rpack ( UFP r,
u32  ins,
u32  dp 
) [private]

Round and pack IEEE floating-point value.

Converts sign, exponent and fraction components to an IEEE floating point value.

Much of the treachery of the IEEE standard is buried here:

  • Rounding modes (chopped, +infinity, nearest, -infinity).
  • Inexact (set if there are any rounding bits, regardless of rounding).
  • Overflow (result is infinite if rounded, max if not).
  • Underflow (no denorms!).
Underflow handling is particularly complicated:
  • Result is always 0.
  • UNF and INE are always set in FPCR.
  • If /U is set,
    • If /S is clear, trap.
    • If /S is set, UNFD is set, but UNFZ is clear, ignore UNFD and trap, because the hardware cannot produce denormals.
    • If /S is set, UNFD is set, and UNFZ is set, do not trap.
  • If /SUI is set, and INED is clear, trap
Parameters:
r Pointer to the unpacked-floating-point UFP structure to be packed.
ins The instruction currently being executed. Used to properly handle exceptions and to determine the rounding mode.
dp DT_S for S-floating or DT_T for T-floating.
Returns:
IEEE floating.

Definition at line 845 of file AlphaCPU_ieeefloat.cpp.

References ufp::exp, FMINF, FMMAX, CAlphaCPU::SCPU_state::fpcr, FPCR_GETFRND, FPCR_INED, FPCR_OVFD, FPCR_UNDZ, FPCR_UNFD, FPINF, FPMAX, FPR_FRAC, FPR_GUARD, FPR_V_EXP, FPR_V_SIGN, ufp::frac, I_FRND_D, I_FRND_M, I_FRND_N, I_FRND_P, I_FTRP_U, I_GETFRND, ieee_trap(), Q_SUI, S_BIAS, S_M_EXP, ufp::sign, state, T_BIAS, T_M_EXP, TRAP_INE, TRAP_OVF, TRAP_UNF, UF_NM, UF_SINF, UF_SRND, UF_TINF, UF_TRND, and X64_QUAD.

Referenced by ieee_cvtif(), ieee_cvtst(), ieee_cvtts(), ieee_fadd(), ieee_fdiv(), ieee_fmul(), and ieee_sqrt().

void CAlphaCPU::ieee_trap ( u64  trap,
u32  instenb,
u64  fpcrdsb,
u32  ins 
) [private]

Set IEEE floating-point trap.

Called when a IEEE floating-point operation detects an exception.

Parameters:
trap A bitmask in which the bits are set that correspond to the exception that occurred.
instenb True if the exception is enabled in the instruction.
fpcrdsb A bitmask containing the bits that, if set in the floating- point control register (fpcr), disable the trap.
ins The instruction currently being executed. Used to properly set some registers for the trap to be handled.

Definition at line 915 of file AlphaCPU_ieeefloat.cpp.

References ARITH_TRAP, CAlphaCPU::SCPU_state::fpcr, I_FTRP_S, I_GETRC, state, TRAP_SWC, and U64.

Referenced by ieee_cvtfi(), ieee_fadd(), ieee_fcmp(), ieee_fdiv(), ieee_fmul(), ieee_rpack(), ieee_sqrt(), and ieee_unpack().

u64 CAlphaCPU::vax_ldf ( u32  op  )  [private]

Convert the VAX F-floating memory format to the VAX floating register format.

Adjust the exponent base, reorder the bytes of the fraction to compensate for the VAX byte-order, and widen the exponent and fraction fields.

Parameters:
op 32-bit VAX F-floating value in memory format.
Returns:
The value op converted to 64-bit VAX floating in register format.

Definition at line 98 of file AlphaCPU_vaxfloat.cpp.

References F_BIAS, F_EXP, F_GETEXP, F_SIGN, F_V_FRAC, FPR_SIGN, FPR_V_EXP, G_BIAS, and SWAP_VAXF.

u64 CAlphaCPU::vax_ldg ( u64  op  )  [private]

Convert the VAX G-floating memory format to the VAX floating register format.

Reorder the bytes to compensate for the VAX byte-order.

Parameters:
op 64-bit VAX G-floating value in memory format.
Returns:
The value op converted to 64-bit VAX floating in register format.

Definition at line 119 of file AlphaCPU_vaxfloat.cpp.

References SWAP_VAXG.

u32 CAlphaCPU::vax_stf ( u64  op  )  [private]

Convert the VAX floating register format to the VAX F-floating memory format.

Adjust the exponent base, make the exponent and fraction fields smaller, and reorder the bytes of the fraction to compensate for the VAX byte-order.

Parameters:
op 64-bit VAX floating in register format.
Returns:
The value op converted to 32-bit VAX F-floating value in memory format.

Definition at line 134 of file AlphaCPU_vaxfloat.cpp.

References F_BIAS, F_EXP, F_SIGN, F_V_EXP, F_V_FRAC, FPR_GETEXP, FPR_GETSIGN, G_BIAS, and SWAP_VAXF.

u64 CAlphaCPU::vax_stg ( u64  op  )  [private]

Convert the VAX floating register format to the VAX G-floating memory format.

Reorder the bytes to compensate for the VAX byte-order.

Parameters:
op 64-bit VAX floating in register format.
Returns:
The value op converted to 64-bit VAX G-floating value in memory format.

Definition at line 161 of file AlphaCPU_vaxfloat.cpp.

References SWAP_VAXG.

void CAlphaCPU::vax_trap ( u64  mask,
u32  ins 
) [private]

Set VAX floating-point trap.

Called when a VAX floating-point operation detects an exception.

Parameters:
mask A bitmask in which the bits are set that correspond to the exception that occurred.
ins The instruction currently being executed. Used to properly set some registers for the trap to be handled.

Definition at line 455 of file AlphaCPU_vaxfloat.cpp.

References ARITH_TRAP, I_FTRP_S, I_GETRC, and TRAP_SWC.

Referenced by vax_cvtfi(), vax_fdiv(), vax_rpack(), vax_rpack_d(), vax_sqrt(), vax_unpack(), and vax_unpack_d().

void CAlphaCPU::vax_unpack ( u64  op,
UFP r,
u32  ins 
) [private]

Unpack VAX floating-point value.

Converts a VAX floating-point value to it's sign, exponent and fraction components.

Parameters:
op 64-bit VAX floating in register format.
r Pointer to the unpacked-floating-point UFP structure where the results are to be returned.
ins The instruction currently being executed. Used to properly handle exceptions.

Definition at line 472 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, FPR_GETEXP, FPR_GETFRAC, FPR_GETSIGN, FPR_GUARD, FPR_HB, ufp::frac, ufp::sign, TRAP_INV, and vax_trap().

Referenced by vax_cvtfi(), vax_fadd(), vax_fcmp(), vax_fdiv(), vax_fmul(), and vax_sqrt().

void CAlphaCPU::vax_unpack_d ( u64  op,
UFP r,
u32  ins 
) [private]

Unpack VAX D-floating-point value.

Converts a VAX D-floating-point value to it's sign, exponent and fraction components.

Parameters:
op 64-bit VAX D-floating in register format.
r Pointer to the unpacked-floating-point UFP structure where the results are to be returned.
ins The instruction currently being executed. Used to properly handle exceptions.

Definition at line 503 of file AlphaCPU_vaxfloat.cpp.

References D_BIAS, ufp::exp, FDR_GETEXP, FDR_GETFRAC, FDR_GETSIGN, FDR_GUARD, FDR_HB, ufp::frac, G_BIAS, ufp::sign, TRAP_INV, and vax_trap().

void CAlphaCPU::vax_norm ( UFP r  )  [private]

Normalize VAX floating-point value.

Normalize exponent and fraction components.

Parameters:
r Pointer to the unpacked-floating-point UFP structure containing the value to be normalized, and where the results are to be returned.

Definition at line 530 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, ufp::frac, ufp::sign, U64, UF_NM, and X64_QUAD.

Referenced by vax_cvtif(), vax_fadd(), vax_fdiv(), and vax_fmul().

u64 CAlphaCPU::vax_rpack ( UFP r,
u32  ins,
u32  dp 
) [private]

Round and pack VAX floating-point value.

Converts sign, exponent and fraction components to a register-format VAX floating point value.

Parameters:
r Pointer to the unpacked-floating-point UFP structure to be packed.
ins The instruction currently being executed. Used to properly handle exceptions and to determine the rounding mode.
dp DT_F for F-floating or DT_G for G-floating.
Returns:
64-bit VAX floating in register format.

Definition at line 573 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, F_BIAS, F_M_EXP, FPR_FRAC, FPR_GUARD, FPR_V_EXP, FPR_V_SIGN, ufp::frac, G_BIAS, G_M_EXP, I_FTRP_V, I_GETFRND, ufp::sign, TRAP_OVF, TRAP_UNF, UF_FRND, UF_GRND, UF_NM, vax_trap(), and X64_QUAD.

Referenced by vax_cvtif(), vax_fadd(), vax_fdiv(), vax_fmul(), and vax_sqrt().

u64 CAlphaCPU::vax_rpack_d ( UFP r,
u32  ins 
) [private]

Round and pack VAX D-floating-point value.

Converts sign, exponent and fraction components to a register-format VAX D-floating-point value.

Parameters:
r Pointer to the unpacked-floating-point UFP structure to be packed.
ins The instruction currently being executed. Used to properly handle exceptions.
Returns:
64-bit VAX D-floating in register format.

Definition at line 620 of file AlphaCPU_vaxfloat.cpp.

References D_BIAS, ufp::exp, FDR_FRAC, FDR_GUARD, FDR_M_EXP, FDR_V_EXP, FDR_V_SIGN, ufp::frac, G_BIAS, I_FTRP_V, ufp::sign, TRAP_OVF, TRAP_UNF, and vax_trap().

int CAlphaCPU::vax_fcmp ( u64  s1,
u64  s2,
u32  ins 
) [private]

Compare 2 VAX floating-point values.

Parameters:
s1 First 64-bit VAX floating in register format to be compared.
s1 Second 64-bit VAX floating in register format to be compared.
ins The instruction currently being executed. Used to properly handle exceptions.
Returns:
0 if s1==s2, 1 if s1>s2, -1 if s1<s2.

Definition at line 186 of file AlphaCPU_vaxfloat.cpp.

References ufp::sign, and vax_unpack().

u64 CAlphaCPU::vax_cvtif ( u64  val,
u32  ins,
u32  dp 
) [private]

Convert 64-bit signed integer to VAX floating-point value.

Parameters:
val 64-bit signed integer to be converted.
ins The instruction currently being executed. Used to properly handle exceptions and to determine the rounding mode.
dp DT_F for F-floating or DT_G for G-floating.
Returns:
64-bit VAX floating in register format.

Definition at line 210 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, ufp::frac, G_BIAS, NEG_Q, ufp::sign, vax_norm(), and vax_rpack().

u64 CAlphaCPU::vax_cvtfi ( u64  op,
u32  ins 
) [private]

Convert VAX floating-point value to 64-bit signed integer.

Note that rounding cannot cause a carry unless the fraction has been shifted right at least FP_GUARD places; in which case a carry out is impossible

Parameters:
op 64-bit VAX floating in register format to be converted.
ins The instruction currently being executed. Used to properly handle exceptions.
Returns:
64-bit signed integer.

Definition at line 240 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, ufp::frac, G_BIAS, I_FTRP_V, I_GETFRND, IMMAX, IPMAX, NEG_Q, ufp::sign, TRAP_IOV, UF_V_NM, vax_trap(), vax_unpack(), and X64_QUAD.

u64 CAlphaCPU::vax_fadd ( u64  s1,
u64  s2,
u32  ins,
u32  dp,
bool  sub 
) [private]

Add or subtract 2 VAX floating-point values.

Parameters:
s1 Augend or minuend in 64-bit VAX floating register format.
s2 Addend or subtrahend in 64-bit VAX floating register format.
ins The instruction currently being executed. Used to properly handle exceptions.
dp DT_F for F-floating or DT_G for G-floating.
sub subtract if true, add if false.
Returns:
64-bit VAX floating in register format.

Definition at line 283 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, ufp::frac, ufp::sign, UF_NM, vax_norm(), vax_rpack(), vax_unpack(), and X64_QUAD.

u64 CAlphaCPU::vax_fmul ( u64  s1,
u64  s2,
u32  ins,
u32  dp 
) [private]

Multiply 2 VAX floating-point values.

Parameters:
s1 Multiplicand in 64-bit VAX floating register format.
s2 Multiplier in 64-bit VAX floating register format.
ins The instruction currently being executed. Used to properly handle exceptions.
dp DT_F for F-floating or DT_G for G-floating.
Returns:
64-bit VAX floating in register format.

Definition at line 351 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, ufp::frac, G_BIAS, ufp::sign, uemul64(), vax_norm(), vax_rpack(), and vax_unpack().

u64 CAlphaCPU::vax_fdiv ( u64  s1,
u64  s2,
u32  ins,
u32  dp 
) [private]

Divide 2 VAX floating-point values.

Needs to develop at least one rounding bit. Since the first divide step can fail, develop 2 more bits than the precision of the fraction.

Parameters:
s1 Dividend in 64-bit VAX floating register format.
s2 Divisor in 64-bit VAX floating register format.
ins The instruction currently being executed. Used to properly handle exceptions.
dp DT_F for F-floating or DT_G for G-floating.
Returns:
64-bit VAX floating in register format.

Definition at line 382 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, ufp::frac, G_BIAS, ufp::sign, TRAP_DZE, ufdiv64(), vax_norm(), vax_rpack(), vax_trap(), and vax_unpack().

u64 CAlphaCPU::vax_sqrt ( u64  op,
u32  ins,
u32  dp 
) [private]

Determine principal square root of a VAX floating-point value.

Parameters:
op 64-bit VAX floating in register format.
ins The instruction currently being executed. Used to properly handle exceptions.
dp DT_F for F-floating or DT_G for G-floating.
Returns:
64-bit VAX floating in register format.

Definition at line 416 of file AlphaCPU_vaxfloat.cpp.

References ufp::exp, ufp::frac, fsqrt64(), G_BIAS, ufp::sign, TRAP_INV, vax_rpack(), vax_trap(), and vax_unpack().

void CAlphaCPU::vmspal_call_cflush (  )  [private]

Implementation of CALL_PAL CFLUSH opcode.

Definition at line 222 of file AlphaCPU_vmspal.cpp.

void CAlphaCPU::vmspal_call_draina (  )  [private]

Implementation of CALL_PAL DRAINA opcode.

Definition at line 231 of file AlphaCPU_vmspal.cpp.

void CAlphaCPU::vmspal_call_ldqp (  )  [private]

Implementation of CALL_PAL LDQP opcode.

Definition at line 240 of file AlphaCPU_vmspal.cpp.

References hw_ldq, r0, and r16.

void CAlphaCPU::vmspal_call_stqp (  )  [private]

Implementation of CALL_PAL STQP opcode.

Definition at line 248 of file AlphaCPU_vmspal.cpp.

References hw_stq, r16, and r17.

void CAlphaCPU::vmspal_call_swpctx (  )  [private]

void CAlphaCPU::vmspal_call_mfpr_asn (  )  [private]

Implementation of CALL_PAL MFPR_ASN opcode.

Definition at line 308 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::asn, r0, and state.

void CAlphaCPU::vmspal_call_mtpr_asten (  )  [private]

Implementation of CALL_PAL MTPR_ASTEN opcode.

Definition at line 316 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::aster, CAlphaCPU::SCPU_state::check_int, r0, r16, and state.

void CAlphaCPU::vmspal_call_mtpr_astsr (  )  [private]

Implementation of CALL_PAL MTPR_ASTSR opcode.

Definition at line 327 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::astrr, CAlphaCPU::SCPU_state::check_int, r0, r16, and state.

void CAlphaCPU::vmspal_call_cserve (  )  [private]

Implementation of CALL_PAL CSERVE opcode.

Definition at line 338 of file AlphaCPU_vmspal.cpp.

References hw_ldl, hw_ldq, hw_stl, p21, p23, CAlphaCPU::SCPU_state::pc, r0, r16, r17, r18, set_pc(), and state.

void CAlphaCPU::vmspal_call_mfpr_fen (  )  [private]

Implementation of CALL_PAL MFPR_FEN opcode.

Definition at line 365 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::fpen, r0, and state.

void CAlphaCPU::vmspal_call_mtpr_fen (  )  [private]

Implementation of CALL_PAL MTPR_FEN opcode.

Definition at line 373 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::fpen, hw_ldq, hw_stl, p21, p4, r16, and state.

void CAlphaCPU::vmspal_call_mfpr_ipl (  )  [private]

Implementation of CALL_PAL MFPR_IPL opcode.

Definition at line 383 of file AlphaCPU_vmspal.cpp.

References p22, and r0.

void CAlphaCPU::vmspal_call_mtpr_ipl (  )  [private]

void CAlphaCPU::vmspal_call_mfpr_mces (  )  [private]

Implementation of CALL_PAL MFPR_MCES opcode.

Definition at line 408 of file AlphaCPU_vmspal.cpp.

References p22, and r0.

void CAlphaCPU::vmspal_call_mtpr_mces (  )  [private]

Implementation of CALL_PAL MTPR_MCES opcode.

Definition at line 416 of file AlphaCPU_vmspal.cpp.

References p22, r16, and U64.

void CAlphaCPU::vmspal_call_mfpr_pcbb (  )  [private]

Implementation of CALL_PAL MFPR_PCBB opcode.

Definition at line 426 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_mfpr_prbr (  )  [private]

Implementation of CALL_PAL MFPR_PRBR opcode.

Definition at line 434 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_mtpr_prbr (  )  [private]

Implementation of CALL_PAL MTPR_PRBR opcode.

Definition at line 442 of file AlphaCPU_vmspal.cpp.

References hw_stq, p21, and r16.

void CAlphaCPU::vmspal_call_mfpr_ptbr (  )  [private]

Implementation of CALL_PAL MFPR_PTBR opcode.

Definition at line 450 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_mfpr_scbb (  )  [private]

Implementation of CALL_PAL MFPR_SCBB opcode.

Definition at line 459 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_mtpr_scbb (  )  [private]

Implementation of CALL_PAL MTPR_SCBB opcode.

Definition at line 468 of file AlphaCPU_vmspal.cpp.

References hw_stq, p21, r16, and U64.

void CAlphaCPU::vmspal_call_mtpr_sirr (  )  [private]

Implementation of CALL_PAL MTPR_SIRR opcode.

Definition at line 476 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::check_int, r16, CAlphaCPU::SCPU_state::sir, and state.

void CAlphaCPU::vmspal_call_mfpr_sisr (  )  [private]

Implementation of CALL_PAL MFPR_SISR opcode.

Definition at line 488 of file AlphaCPU_vmspal.cpp.

References r0, CAlphaCPU::SCPU_state::sir, and state.

void CAlphaCPU::vmspal_call_mfpr_tbchk (  )  [private]

Implementation of CALL_PAL MFPR_TBCHK opcode.

Definition at line 496 of file AlphaCPU_vmspal.cpp.

References r0, and U64.

void CAlphaCPU::vmspal_call_mtpr_tbia (  )  [private]

Implementation of CALL_PAL MTPR_TBIA opcode.

Definition at line 504 of file AlphaCPU_vmspal.cpp.

References ACCESS_EXEC, ACCESS_READ, flush_icache(), and tbia().

void CAlphaCPU::vmspal_call_mtpr_tbiap (  )  [private]

Implementation of CALL_PAL MTPR_TBIAP opcode.

Definition at line 514 of file AlphaCPU_vmspal.cpp.

References ACCESS_EXEC, ACCESS_READ, flush_icache_asm(), and tbiap().

void CAlphaCPU::vmspal_call_mtpr_tbis (  )  [private]

Implementation of CALL_PAL MTPR_TBIS opcode.

Definition at line 524 of file AlphaCPU_vmspal.cpp.

References ACCESS_EXEC, ACCESS_READ, r16, and tbis().

void CAlphaCPU::vmspal_call_mfpr_esp (  )  [private]

Implementation of CALL_PAL MFPR_ESP opcode.

Definition at line 533 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_mtpr_esp (  )  [private]

Implementation of CALL_PAL MTPR_ESP opcode.

Definition at line 543 of file AlphaCPU_vmspal.cpp.

References hw_ldq, hw_stq, p21, and r16.

void CAlphaCPU::vmspal_call_mfpr_ssp (  )  [private]

Implementation of CALL_PAL MFPR_SSP opcode.

Definition at line 553 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_mtpr_ssp (  )  [private]

Implementation of CALL_PAL MTPR_SSP opcode.

Definition at line 563 of file AlphaCPU_vmspal.cpp.

References hw_ldq, hw_stq, p21, and r16.

void CAlphaCPU::vmspal_call_mfpr_usp (  )  [private]

Implementation of CALL_PAL MFPR_USP opcode.

Definition at line 573 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_mtpr_usp (  )  [private]

Implementation of CALL_PAL MTPR_USP opcode.

Definition at line 583 of file AlphaCPU_vmspal.cpp.

References hw_ldq, hw_stq, p21, and r16.

void CAlphaCPU::vmspal_call_mtpr_tbisd (  )  [private]

Implementation of CALL_PAL MTPR_TBISD opcode.

Definition at line 593 of file AlphaCPU_vmspal.cpp.

References ACCESS_READ, r16, and tbis().

void CAlphaCPU::vmspal_call_mtpr_tbisi (  )  [private]

Implementation of CALL_PAL MTPR_TBISI opcode.

Definition at line 601 of file AlphaCPU_vmspal.cpp.

References ACCESS_EXEC, r16, and tbis().

void CAlphaCPU::vmspal_call_mfpr_asten (  )  [private]

Implementation of CALL_PAL MFPR_ASTEN opcode.

Definition at line 609 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::aster, r0, and state.

void CAlphaCPU::vmspal_call_mfpr_astsr (  )  [private]

Implementation of CALL_PAL MFPR_ASTSR opcode.

Definition at line 617 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::astrr, r0, and state.

void CAlphaCPU::vmspal_call_mfpr_vptb (  )  [private]

Implementation of CALL_PAL MFPR_VPTB opcode.

Definition at line 625 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_mtpr_datfx (  )  [private]

Implementation of CALL_PAL MTPR_DATFX opcode.

Definition at line 633 of file AlphaCPU_vmspal.cpp.

References hw_ldq, hw_stq, p21, r16, and U64.

void CAlphaCPU::vmspal_call_mfpr_whami (  )  [private]

Implementation of CALL_PAL MFPR_WHAMI opcode.

Definition at line 648 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_imb (  )  [private]

Implementation of CALL_PAL IMB opcode.

Definition at line 656 of file AlphaCPU_vmspal.cpp.

References flush_icache(), hw_ldl, hw_ldq, hw_stl, p20, p21, p22, and p5.

void CAlphaCPU::vmspal_call_prober (  )  [private]

Implementation of CALL_PAL PROBER opcode.

Definition at line 672 of file AlphaCPU_vmspal.cpp.

References ACCESS_READ, ALT, CAlphaCPU::SCPU_state::alt_cm, hw_stq, p21, p22, p23, p4, p5, p6, CAlphaCPU::SCPU_state::pc, PROBE, r0, r16, r17, r18, state, and virt2phys().

void CAlphaCPU::vmspal_call_probew (  )  [private]

Implementation of CALL_PAL PROBEW opcode.

Definition at line 700 of file AlphaCPU_vmspal.cpp.

References ACCESS_WRITE, ALT, CAlphaCPU::SCPU_state::alt_cm, hw_stq, p21, p22, p23, p4, p5, p6, CAlphaCPU::SCPU_state::pc, PROBE, PROBEW, r0, r16, r17, r18, state, and virt2phys().

void CAlphaCPU::vmspal_call_rd_ps (  )  [private]

Implementation of CALL_PAL RD_PS opcode.

Definition at line 727 of file AlphaCPU_vmspal.cpp.

References p22, r0, and U64.

int CAlphaCPU::vmspal_call_rei (  )  [private]

void CAlphaCPU::vmspal_call_swasten (  )  [private]

Implementation of CALL_PAL SWASTEN opcode.

Definition at line 850 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::aster, CAlphaCPU::SCPU_state::check_int, p22, r0, r16, and state.

void CAlphaCPU::vmspal_call_wr_ps_sw (  )  [private]

Implementation of CALL_PAL WR_PS_SW opcode.

Definition at line 865 of file AlphaCPU_vmspal.cpp.

References p22, r16, and U64.

void CAlphaCPU::vmspal_call_rscc (  )  [private]

Implementation of CALL_PAL RSCC opcode.

Definition at line 874 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::cc, hw_ldq, hw_stq, p21, r0, state, and U64.

void CAlphaCPU::vmspal_call_read_unq (  )  [private]

Implementation of CALL_PAL READ_UNQ opcode.

Definition at line 887 of file AlphaCPU_vmspal.cpp.

References hw_ldq, p21, and r0.

void CAlphaCPU::vmspal_call_write_unq (  )  [private]

Implementation of CALL_PAL WRITE_UNQ opcode.

Definition at line 897 of file AlphaCPU_vmspal.cpp.

References hw_ldq, hw_stq, p21, and r16.

int CAlphaCPU::vmspal_ent_dtbm_double_3 ( int  flags  )  [private]

int CAlphaCPU::vmspal_ent_dtbm_single ( int  flags  )  [private]

int CAlphaCPU::vmspal_ent_itbm ( int  flags  )  [private]

int CAlphaCPU::vmspal_ent_iacv ( int  flags  )  [private]

Entry point for IStream Access Violation.

Definition at line 1524 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::current_pc, hw_stq, p20, p21, p23, p4, p5, p6, p7, set_pc(), state, and vmspal_int_initiate_exception().

Referenced by virt2phys().

int CAlphaCPU::vmspal_ent_dfault ( int  flags  )  [private]

int CAlphaCPU::vmspal_ent_ext_int ( int  ei  )  [private]

int CAlphaCPU::vmspal_ent_sw_int ( int  si  )  [private]

int CAlphaCPU::vmspal_ent_ast_int ( int  ast  )  [private]

int CAlphaCPU::vmspal_int_initiate_exception (  )  [private]

int CAlphaCPU::vmspal_int_initiate_interrupt (  )  [private]

Pass control to the OS for handling the interrupt.

Definition at line 971 of file AlphaCPU_vmspal.cpp.

References CAlphaCPU::SCPU_state::cm, hw_ldq, hw_stq, p20, p21, p22, p4, p5, p6, p7, CAlphaCPU::SCPU_state::r, r1, r2, r3, r30, set_pc(), state, stq, and U64.

Referenced by vmspal_ent_ast_int(), vmspal_ent_ext_int(), and vmspal_ent_sw_int().


Field Documentation

Definition at line 298 of file AlphaCPU.h.

Referenced by check_state(), init(), start_threads(), and stop_threads().

Definition at line 299 of file AlphaCPU.h.

Referenced by release_threads(), run(), start_threads(), and stop_threads().

bool CAlphaCPU::StopThread [private]

Definition at line 300 of file AlphaCPU.h.

Referenced by run(), start_threads(), and stop_threads().

bool CAlphaCPU::icache_enabled [private]

Definition at line 414 of file AlphaCPU.h.

Referenced by check_state(), execute(), and init().

Definition at line 415 of file AlphaCPU.h.

Referenced by init().

Definition at line 416 of file AlphaCPU.h.

Referenced by init().

Definition at line 417 of file AlphaCPU.h.

Referenced by check_state().

Definition at line 418 of file AlphaCPU.h.

Referenced by check_state(), and init().

Definition at line 419 of file AlphaCPU.h.

Referenced by check_state(), and init().

Definition at line 420 of file AlphaCPU.h.

Referenced by check_state(), and init().

Definition at line 421 of file AlphaCPU.h.

Referenced by check_state(), execute(), and init().

Definition at line 422 of file AlphaCPU.h.

Referenced by execute(), and init().

Definition at line 423 of file AlphaCPU.h.

Referenced by execute(), and init().

Definition at line 424 of file AlphaCPU.h.

Referenced by check_state(), get_speed(), and init().

Physical address of current instruction.

Definition at line 529 of file AlphaCPU.h.

Referenced by get_icache().

Definition at line 530 of file AlphaCPU.h.

Referenced by execute(), and get_last_instruction().


The documentation for this class was generated from the following files:

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